|Mfr||Lattice Semiconductor Corporation|
|Number of LABs/CLBs||625|
|Number of Logic Elements/Cells||5000|
|Total RAM Bits||169984|
|Number of I/O||146|
|Voltage - Supply||1.14V ~ 1.26V|
|Mounting Type||Surface Mount|
|Operating Temperature||-40°C ~ 125°C (TJ)|
|Package / Case||208-BFQFP|
|Supplier Device Package||208-PQFP (28x28)|
|Base Product Number||LAXP2|
LAXP2-5E-5QN208E Datasheet Download
The LAXP2-5E-5QN208E is a high-performance, low-power, low-cost field-programmable gate array (FPGA) chip model designed by Lattice Semiconductor Corporation. It is designed to meet the needs of a wide range of applications, including industrial, automotive, medical, telecommunications, and consumer applications.
The chip model is based on the LatticeXP2-5E family of FPGAs and includes a 5-bit embedded memory, a 5-bit embedded non-volatile memory, and a 5-bit embedded non-volatile memory controller. It features a 5-bit embedded SRAM, a 5-bit embedded ROM, and a 5-bit embedded flash memory. The chip also features a high-speed serial interface, a high-speed parallel interface, and a high-speed logic interface.
The chip model is capable of delivering high-performance, low-power operation with an operating voltage of 0.9V to 1.2V and a maximum power consumption of 4.5W. It also features a wide range of configurable I/Os, including LVDS, LVCMOS, and PCI Express.
The chip model is suitable for a wide range of applications, including industrial, automotive, medical, telecommunications, and consumer applications. It is designed to provide a cost-effective solution for a wide range of applications, including high-speed communications, video processing, image processing, and digital signal processing. In addition, it is suitable for a wide range of applications, including embedded systems, networking, and system-on-chip (SoC) designs.
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