ISPLSI2064VE-280LB100
ISPLSI2064VE-280LB100
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rohs
Lattice

ISPLSI2064VE-280LB100


ISPLSI2064VE-280LB100
F11-ISPLSI2064VE-280LB100
Active
EE PLD, 5.5 ns, 64-Cell, CMOS, 10 X 10 MM, 0.80 MM PITCH, CABGA-100
10 X 10 MM, 0.80 MM PITCH, CABGA-100

ISPLSI2064VE-280LB100 ECAD Model


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ISPLSI2064VE-280LB100 Attributes


Type Description Select
Rohs Code No
Part Life Cycle Code Obsolete
Supply Voltage-Nom 3.3 V
Propagation Delay 5.5 ns
Number of Macro Cells 64
Number of I/O Lines 64
Programmable Logic Type EE PLD
Temperature Grade COMMERCIAL
Package Shape SQUARE
Technology CMOS
Organization 0 DEDICATED INPUTS, 64 I/O
Additional Feature YES
Clock Frequency-Max 182 MHz
In-System Programmable YES
JTAG BST NO
Output Function MACROCELL
Power Supplies 3.3 V
Supply Voltage-Max 3.6 V
Supply Voltage-Min 3 V
JESD-30 Code S-PBGA-B100
Qualification Status Not Qualified
JESD-609 Code e0
Moisture Sensitivity Level 3
Operating Temperature-Max 70 °C
Peak Reflow Temperature (Cel) 240
Time@Peak Reflow Temperature-Max (s) 30
Number of Terminals 100
Package Body Material PLASTIC/EPOXY
Package Code LFBGA
Package Equivalence Code QFP100,.63SQ,20
Package Shape SQUARE
Package Style GRID ARRAY, LOW PROFILE, FINE PITCH
Surface Mount YES
Terminal Finish TIN LEAD
Terminal Form BALL
Terminal Pitch 800 µm
Terminal Position BOTTOM
Width 10 mm
Length 10 mm
Seated Height-Max 1.5 mm
Ihs Manufacturer LATTICE SEMICONDUCTOR CORP
Part Package Code BGA
Package Description 10 X 10 MM, 0.80 MM PITCH, CABGA-100
Pin Count 100
Reach Compliance Code not_compliant
HTS Code 8542.39.00.01

ISPLSI2064VE-280LB100 Datasheet Download


ISPLSI2064VE-280LB100 Overview


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